This invention relates to a circuit for use in testing a logic circuit such as an integrated circuit (IC) or a large scaled integrated circuit (LSI), more particularly, to a circuit for use in testing the logic circuit by scan path.
In general, it is known in the art that scan path is used on testing a logic circuit such as an integrated circuit (IC) or a large scaled integrated circuit (LSI). The scan path may be composed of flip-flops and latch circuits. More particularly, the logic circuit is located on a substrate together with scan paths which are connected in serial to one another. Such a logic circuit will be called a logic package. The logic circuit has a plurality of input/output (I/O) pins. The I/O pins of the logic circuit is connected to tester pins of a tester, respectively, on testing the logic circuit. Therefore, it is necessary to increase the number of the tester pins as the number of the I/O pins in the logic circuit becomes great. However, it is difficult to increase the number of tester pins as the number of the I/O pins increases. In other words, it is difficult to test a logic circuit having a number of I/O pins.
In order to easily test the logic circuit having a number of I/O pins, it is known In the art that a scan path circuit is used in testing the logic circuit.
It will be assumed that the logic package has a plurality of first scan paths and the scan path circuit has a plurality of second scan paths which is equal in structure to the first scan paths, respectively. The scan path circuit is located between the logic package and the tester. More particularly, the second scan paths of the scan path circuit are directly connected to the I/O pins of the logic circuit in a conventional scan path circuit, respectively. It is impossible to normally test the logic circuit as will be described later when the conventional scan path circuit is located between the logic package and the tester.